By Norman G. Einspruch
Includes contributions from a dozen pros from the inner most zone and academia. Discusses numerous gadget physics themes of specific curiosity to and collage researchers in electric engineering, computing device technological know-how, and digital fabrics. Emphasizes actual description, mode
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Publication through Friedman, Norman
A set of articles taken from ''EDN'' electronics journal, designed to maintain training electronics engineers abreast of contemporary advancements within the fields of pcs, microcontrollers and different electronic undefined. The essays concentrate on details pertinent to analog circuit layout
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Additional resources for Advanced MOS Device Physics
K. Ko, and J. L. Moll, The effect of high fields on MOS device and circuit performance. IEEE Trans. Electron Devices ED-31(10), 1386 (1984). 33. M. C. Jeng, J. Chung, A. Wu, J. Moon, T. Y. Chan, G. May, P. K. Ko, and C. Hu, Performance and reliability of deep-submicron M O S F E T s . Tech. —Int. , p. 710 (1987). 34. S. Y. Chou and D. A. Antoniadias, Relationship between measured and intrinsic transcon ductance of FETs. IEEE Trans. Electron Devices ED-34, 448 (1987). 35. T. Toyabe et al, A numerical model of avalanche breakdown in MOSFETs.
In particular, the buried-channel nature of the devices can lead to p o o r turn-off characteristics. However, in normal circuit applications, the depletion-mode transistors are never turned off, and so this does not necessarily present a problem. Short-channel effects in buried-channel P M O S devices are dis cussed in Section III, and in general the same principles can be applied to N M O S devices with appropriate changes in d o p a n t types. III. p-CHANNEL M O S TRANSISTORS In advanced M O S technologies, p-channel transistors are used exclusively in C M O S logic or analog circuits.
It is thus clear that the art of process integration requires good knowledge of device physics, process capabilities, and circuit design issues. Historically, the trend in process integration has been toward increasing complexity as device dimensions have been reduced. Early N M O S tech nologies required only four masks. The move to include depletion load devices added another couple of masks, while multilevel metallization required a pair of masks for each additional level. -channel devices on the same substrate.